Using Electro Optical Terahertz Pulse Reflectometry to Isolate Faults in 3D IC Packages

Table of Contents

Results and Discussion


In recent years, 3D IC package designs have become widespread due to their ability to integrate increasingly logical circuits within the same footprint as their traditional, two dimensional counterparts. However, the failure analysis community faces new challenges from increased circuit complexity. Time Domain Reflectometry (TDR) measurements are traditionally used for defect prelocalization. A typical TDR workflow involves comparison of measurement from a failed device with a reference Known Good Device (KGD), where the fault location is determined from the timing information embedded in these measurements.

Producing golden KGDs for the comparative study and interpreting the measurement results based on time-based information alone has become increasingly difficult due to the scale up in circuit complexity. Electro Optical Terahertz Pulse Reflectometry (EOTPR), an implementation of the TDR technique at terahertz frequencies, has been proven to improve fault isolation accuracy to <10 µm [1, 2, 3, 4]. This improvement is achieved through a step increase in temporal resolution and reduction in measurement jitter noise [1]. During operation, a high frequency circuit probe is used to launch electrical pulses into the device-under-test (DUT). A fast photoconductive switch (PCS) records the reflections from device structures and faults as a voltage-time waveform.

In a recent study [5], researchers generated a Virtual Known Good Device (VKGD) using commercial 3D electromagnetic simulation software. Simulation of the EOTPR measurement process provided a reference waveform, which was virtually identical to one measured from a physical KGD. The researchers established a correlation between the waveform features and the key structures in DUT by monitoring the real time pulse propagation in the simulation. The spatial information obtained from the simulation in combination with highly accurate EOTPR measurements can help readily achieve feature-based fault isolation with an accuracy level of less than 10 µm in modern package substrates [5, 6]. This article discusses the use of this fault isolation method on a complex 3D package (Figure 1). This package contains a die and a substrate, where the physical dimensions traces in the constituents differ by over an order of magnitude.

Figure 1. Model of the 3D package consisting of a substrate and (inset) an interposer structure.


An EOTPR system consists of two PCSs; one functioning as an instantaneous current detector that is activated by a mode-locked near infrared laser and the other as an electrical pulse source. The emitted pulse is coupled into the DUT through a high frequency probe and a co-axial cable and the reflected pulse is directed into the PCS detector. The relative delay is swept between the emission and detection timings by a translation stage in the detector beam path (Figure 2), producing a continuous voltage-time waveform for the user. An example waveform from an open probe is shown in Figure 2b. The system response is deconvolved from the measured waveform using a post-processing procedure as in [5] to facilitate meaningful comparison with a model generated reference waveform.

Figure 2. (a) Schematic of an EOTPR system; (b) Typical raw EOTPR waveform from the open end of a high frequency probe.


A commercially available EM simulation tool is used to accurately capture the electromagnetic (EM) response of the DUT. The finite difference time domain (FDTD) method [7] is used to determine the transient EM behaviors through Maxwell’s equations. This method does not require phenomenological quantities, such as inductance and capacitance, and as a result, all inter-conductor couplings behaviors arise naturally.

Figure 1 shows a section of a model of a 3D package produced directly from the DUT design file. The trace displayed in Figure 1 comprises of a ball grid array (BGA) attached to a via column on the substrate side. The signal path continues into the interposer structure through a C4 bump, where a through silicon via (TSV) connects to a top level trace which is terminated by an open pad for a microbump. In this design, the width of the substrate side traces is 60 µm compared to 3 µm wide traces in the interposer.

In this instance, the modeling process comprises of two iterations: VKGD creation for the bare substrate using the procedures outlined in [5] and then VKGD creation for the entire package facilitated by applying the values obtained from the bare substrate model. The die and the substrate are simulated individually to run the second model accurately and within a reasonable time. The inset shown in Figure 1 depicts the split plane where the propagating pulse is extracted from the substrate side model and introduced into the equivalent point of the interposer model.

In a complex structure like the one modeled in this study, considerable cross-coupling can occur between the signal trace and its adjacent neighboring line. Therefore, it is necessary to record the propagating pulse across both parallel traces as it crosses the model split boundary. For each portion of the model, ‘scattering’ S parameters were obtained for coupling along the signal line, and for cross-coupling into the adjacent neighboring lines. During post-processing, these parameters are combined with the equivalent S parameters derived from other model portion to create the VKGD model waveform for the entire stacked package.

Results and Discussion

Figure 3 displays the measured and simulated EOTPR waveforms for the signal trace in: (a) the bare substrate device, and (b) the full package. The measured (red curve) waveforms agree well with the simulated (blue curve) waveforms, enabling the identification of key device design features. The good agreement between the simulated and measured results in Figure 3a indicates that the substrate VKGD is correctly set up. A VKGD is subsequently created for the full package by following the procedures as outlined in [5], with only the die side requiring further attention. From the simulation, it is possible to extract the pulse propagation velocity between key device structures and use them for fault location in a measured device with a simple time-of-flight calculation.

Figure 3. Comparison of simulated and measured EOTPR waveforms in the (a) bare substrate; (b) full package. The red and blue curves show the measured and simulated wave- forms in both cases. The pale gray and green curves in (b) are the measured and simulated waveforms for a failed package. Comparison of the waveform peaks against the brown dotted alignment lines in the two plots clearly indicate that the open fault in the package lies just after the C4 bump.

The simulation results are tested against a failed device in order to validate the technique. The gray curve shown in Figure 3b displays the measured EOTPR waveform from a failed package device. A clear deviation can be observed between this waveform and the reference waveform, with a notable peak at ~ 125 ps. This signifies the presence of an open fault at a considerable distance before the microbump. Calculations based on the pulse propagation velocity from the simulation imply that the waveform peak is a reflection originating from just after the TSV within the interposer. This is followed by the simulation of a subsequent model with a virtual open circuit created at the suggested location, generating the resulting green waveform shown in Figure 3b. The close correspondence with the gray waveform corroborates the accuracy of the simulation technique. Subsequent physical failure analysis (Figure 4) carried out on the failing device confirmed the position of the open fault to be at the top of the TSV. These results corroborate the EOTPR modeling analysis.

Figure 4. SEM images showing the region around the TSV in: (a) A good reference device; (b) the failed device showing the open fault failure at the top of the TSV; (c) close up of the same device around the open failure.


This article has demonstrated that key device design elements can be correlated with EOTPR waveform features using the combination of EOTPR and 3D DUT modeling. It has additionally illustrated how faults can be identified in advanced IC packages without the need for a physical reference device using the combination of EOTPR and DUT simulations.

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