Imaging of a Copper Pillar Cross-section using the TESCAN UHR Triglav™ SEM Column

Copper pillar bumping is intended as a replacement to traditional solder bumping. In the solder bump process, a bump is formed on the chip and on the package substrate and they are connected by reflow. During the reflow the solder bumps collapse and do not retain their height in two directions. Moreover, the solder bumps occupy a larger space than the pitch of a pad on the chip. Copper pillar technology promotes a fine pitch, flip chip process, which is vital for today’s portable devices and for future portable devices.

TESCAN UHR-SEM/Plasma FIB XEIA3 Microscope

The TESCAN UHR-SEM/plasma FIB XEIA3 microscope has been used to prepare and observe copper pillar cross-sections. Cross-sectioning plays a crucial role in failure analysis in the semiconductor industry. A cross-section which has been well prepared will often provide physical evidence of the failure mode. In the case of copper pillar technology, for example, cross-sectioning is ideal for inspecting interfaces and providing evidence of nonwetting or delamination, inspecting the bottoms of etch holes such as vias and contacts and characterizing thin-film metal and interlevel dielectric thicknesses.

Overview of the Cu pillar imaged at 5 keV with the Low-Energy BSE (LE-BSE) detector showing strong material contrast between SnAg, Ni, Cu and the Si substrate.

Figure 1. Overview of the Cu pillar imaged at 5 keV with the Low-Energy BSE (LE-BSE) detector showing strong material contrast between SnAg, Ni, Cu and the Si substrate.

Right corner of the copper pillar. Imaged acquired at 5 keV with the LE-BSE detector shows channelling grain contrast on Cu forming the base of the pillar and top metal Al layer. Inspection of underfill filling quality and under bump metallurgy layers is also possible.

Figure 2. Right corner of the copper pillar. Imaged acquired at 5 keV with the LE-BSE detector shows channelling grain contrast on Cu forming the base of the pillar and top metal Al layer. Inspection of underfill filling quality and under bump metallurgy layers is also possible.

 Detailed image of the transistor and integrated circuit layers located below the pillar. Image acquired at 5 keV with the Mid-Angle BSE detector.

Figure 3. Detailed image of the transistor and integrated circuit layers located below the pillar. Image acquired at 5 keV with the Mid-Angle BSE detector.

This information has been sourced, reviewed and adapted from materials provided by TESCAN.

For more information on this source, please visit Tescan.com.

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