Using EBSD to Improve Reliability in 3-D Integrated Circuits

Materials Challenge

Three-dimensional integrated circuits, or 3D IC, have emerged as a promising path for high-performance systems to satisfy the increasing demands of mobile computing. Multiple device levels are joined into a single integrated circuit through-silicon vias (TSV). This method offers faster device operation, eliminates the need for edge wiring, and reduces power consumption and the electrical path-length.

The reliability of copper TSVs relies on deposition conditions as well as the thermal loading used at the time of the 3D IC manufacturing process. In order to increase the lifetime of the device, the optimization of both deposition and thermal annealing conditions is significant.

Comparison with Existing Solutions

At the time of device fabrication, examining the variations in microstructure that occur as a result of the processing conditions can be a predictor of the TSVs’ reliability in 3D ICs. Using a combination of characterization methods, the microstructural features of interest can be observed:

  • Transmission Electron Microscopy (TEM) — TEM offers crystallographic-based imaging of defects and grains within a TSV. While these images offer qualitative microstructural information, the determination of the crystallographic orientation in the TEM is usually performed manually. This restricts the number of quantitative measurements and makes statistically reliable sampling difficult for grain size and preferred orientation determination.
  • Focused Ion Beam (FIB) — FIB images offer qualitative information on TSV deposition and filling quality and on grain size through crystallographic channeling imaging. FIB imaging does not enable quantitative grain size determination or offer direct crystallographic orientation information. Grain size offers information on the annealing process, while the crystal orientation offers feedback on the deposition process.
  • Nanoindentation — By characterizing material response on a sub-micrometer scale, nanoindentation offers information on elastic moduli and yield strength, providing an understanding of the plastic strain and grain size present within the TSVs. Microstructural features like crystal composition and orientation can change the local strain and strength values measured; however, the variance in measured values cannot be precisely explained without a direct understanding of this local microstructure.

On the contrary, electron backscatter diffraction (EBSD) offers a quick and automated solution for characterizing the microstructure of copper TSVs. The benefits of EBSD are:

  • Uncertainty in grain determination is eliminated by direct measurement of grain size through discrete crystallographic orientation measurements. After deposition and thermal cycling, the grain size of copper can be measured to modify the manufacturing parameters for controlling grain size distribution and obtaining complete TSV fill.
  • A better understanding of the copper film deposition process can be obtained through direct measurement of crystallographic orientation and texture. Variables such as deposition rate, voltage, and bath additives determine the preferred orientation that develops and impacts the fill rate and probability of void formation.
  • Direct measurement of intergranular misorientations that develop within the TSV copper can be realized. These misorientations signify the occurrence of plastic deformation during thermal cycling. The presence of plastic deformation signifies that copper protrusions may form which cause reliability concerns with delamination and cracking.

Microanalysis Results

EBSD data was obtained from a 6 μm x 40 μm copper TSV after deposition and thermal cycling simulating back-end-of-line (BEOL) processing. An orientation map with orientations colored in relation to the sidewall growth direction is demonstrated in Figure 1. The EBSD data shows a recrystallized structure with a lot of twin boundaries without any significant development of preferred orientation.

Moreover, an excellent TSV fill is seen. The average size of the grain is 978 nm. Twin boundaries offer considerably slower diffusion pathways through the TSV in relation to random high-angle grain boundaries. If twin boundaries are eliminated from the grain determination algorithm, then a twin-adjusted grain size of 2.72 μm can be measured. This adjusted grain size will predict the reliability in a much better manner.

Orientation map of copper through-silicon via showing no preferred orientation.

Figure 1. Orientation map of copper through-silicon via showing no preferred orientation.

The grain structure, including and excluding twins, is shown in Figure 2, where the grains are arbitrarily colored to demonstrate morphology and size. The grain structure without twins is closer to the preferred “bamboo” structure, where the high-angle boundaries are typically close to perpendicular to the length of the TSV. This grain structure restricts the possible diffusion paths of grain boundary through the TSV and will offer better electromigration failure resistance.

Grain maps of copper TSV with twin boundaries included and excluded from grain.

Figure 2. Grain maps of copper TSV with twin boundaries included and excluded from grain.

A Kernel Average Misorientation (KAM) map, with coloring relative to the level of plastic deformation present in the copper TSV, is shown in Figure 3. At the time of thermal cycling, the coefficient of thermal expansion differences between the copper and surrounding silicon wafer results in the development of stresses. Permanent plastic deformation will occur when these stresses surpass the elastic limit of the copper. This deformation may result in copper protrusions from within the TSV that can manifest as reliability problems within the device.

Kernel average misorientation map showing the plastic strain developing after thermal cycling, which can reduce reliability.

Figure 3. Kernel average misorientation map showing the plastic strain developing after thermal cycling, which can reduce reliability.

The KAM map shows that a region of plastic deformation has formed at the base of this TSV. In this instance, variables in thermal cycling should be modified to reduce the applied stress for better reliability.

Recommended EDAX Solution

The TEAM™ Pegasus Analysis System can assist engineers in developing deposition and thermal cycling manufacturing procedures for reliable copper TSVs in 3D IC applications. This system provides combined EBSD and EDS characterization with a user-friendly interface for quick analysis of grain size, texture, phase distribution, and grain orientation. Hikari Super EBSD Cameras offer rapid, smart, and sensitive EBSD pattern collection with better orientation precision for measuring plastic deformation within stressed TSVs.

This information has been sourced, reviewed and adapted from materials provided by EDAX Inc.

For more information on this source, please visit EDAX Inc.

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