In 1958, the first working integrated circuit was demonstrated by Jack Kilby whose main priority had been miniaturization. Large, thermally inefficient vacuum tube technology no longer had to be relied upon with the invention of the transistor in 1948. And so, the race to develop the smallest IC could begin.
Over the last 50 years, semiconductor devices have become exponentially smaller. With smartphones, we can hold a computer in the palm of our hands. Given their size, the processing power of these is incredible, as is their low operational temperature. Both these are possible due to the design of the IC and the complex and efficient arrangement of surrounding connectors.
How Packaging is Keeping Up with Advances in Chip Design
Wafer level packaging (WLP) is currently the most significant development in the size reduction of overall chip assembly. The chip and connectors are made as small as possible with this fabrication method. It is the area of the chip itself that sets the limit of the device size.
The effect of packaging on the performance of devices becomes greater as devices become smaller and more complex. To maintain high switching speeds and low operating temperatures, connectors need to be designed to minimize resistance and length. For example, the advantage of flip-chip technology over wirebond packaging is more efficient contact. High-speed connections are impeded by a large density of wires as they cause excessive inductance.
In addition to size and speed, another level of complexity is added by the new generation of Microelectromechanical Systems (MEMS), which can integrate mechanical sensors and electronics within just one chip. New uses for this technology continue to be found. Examples of such applications include accelerometers for air-bag sensors, optical switches and blood pressure sensors. These devices are already very intricate and the sensors add yet more contacts to them. The packaging also becomes a challenge, as part of the sensor requires the usual plating and sealing, yet the remainder must be open to the environment to be effective.
Connections are made via layers of plated metal and a solder is applied to these layers. This is regardless of whether the chip is a standard IC processor or a MEMS device. Ensuring the correct thickness and composition for the layers beneath the solder is crucial. XRF is a form of bump metallurgy (UBM) and is used to validate the integrity of deposited layers to which the solder ‘bumps’ are applied.
Either a lead frame or a PCB can be used to connect the semiconductor device to everything else. Both PCBs and lead frames must have very thin tracks at a high density for smaller devices with more connections. PCBs are now available with tracks as thin as 20 µm. The degree of precision and uniformity required today means that the most advanced lead frames must be laser cut or photo-etched.
Deposited layers on wafers, lead frames and PCBs can all be analyzed through the proven XRF technology. However, the ability of old school XRF to provide reliable results is now being challenged as features become increasingly small.
The XRF Analyzer Designed for WLP Analysis: FT150
Under bump metallurgy, lead frame plating and PCB plating, XRF analyzers have been developed by Hitachi High-Tech that are specifically suited for verifying IC substrates. High-precision measurements of nanometer-scale plating can be delivered with the latest X-ray technology within the FT150 analyzer.
Solder bumps, metal deposits and plating throughout semiconductor fabrication all require highly accurate plating thickness measurements and composition analysis. This is allowed for with a beam diameter of less than 30 µm.
This information has been sourced, reviewed and adapted from materials provided by Hitachi High-Tech Analytical Science.
For more information on this source, please visit Hitachi High-Tech Analytical Science.