Advanced Packaging with Surface Metrology

As any manufacturer of advanced integrated chips (ICs) will tell you, what you see is not always what you get. When fabricating ICs, commonly known as microchips, many of the wafer's key features are so minuscule that even the most advanced optical microscopes cannot observe them in fine detail.

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However, it remains vital that they adhere to the strict tolerances set for fabrication.

With the advent of 3D-integrated chips, the problem has only increased. Products are faster and smaller than ever before as it stacks multiple chips in layers. To maintain functionality, the features of each layer are minuscule, typically just a few microns wide. Since a micron is a millionth of a meter, it is comparable to trying to locate a manhole cover from 600 kilometers away.

TSVs, or Through Silicon Vias, are an excellent case study. They are tunnels that infiltrate each chip layer to provide interconnecting links. TSVs are also exceptionally small, typically in the region of 12 microns wide and 200 microns deep.

Fortunately, ongoing advances in metrology directly improve visibility. Modern systems use light in a completely new way to make the invisible visible. A narrow beam is projected onto the wafer, which is then analyzed using methods to detect even the most minute variations on its surface.

TSV cavities, bumps, and trenches are exposed in excellent detail. In all three dimensions, the user thus receives everything required for confident advancement and manufacture. Recently, FormFactor added an innovative form of metrology to its expanding family of products, a prime example of the company’s commitment to leadership in wafer testing and measurements.

This information has been sourced, reviewed and adapted from materials provided by FormFactor Inc.

For more information on this source, please visit FormFactor Inc.

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