Production of High Efficiency Solar Cells Using ICPCVD and PECVD

The heterojunction with an intrinsic thin layer or HIT solar cell was initially introduced by Sanyo in 1992. The record efficiency for such a cell is presently held by Sanyo and the value is 23% lab efficiency. The fundamental layer structure of a typical HIT cell is shown in figure 1 and can be considered as a hybrid between low cost amorphous silicon, thin film technology and high quality crystalline silicon cells.

HIT cell structure

Figure 1. HIT cell structure

Major Differences Between HIT Cells and Conventional Crystalline Silicon Cells

The main differences between the HIT cell and a more traditional crystalline silicon cell are listed below:

  • Different semiconductor materials are introduced to create the pn-junction and back surface field, an intrinsic layer is introduced and a transparent conducting oxide is added.
  • Hence the HIT cell shows superior conversion efficiency performance compared with traditional crystalline silicon cells when operating at high temperatures.
  • A major advantage in the manufacturing process of HIT cells is that the thermal budget is considerably reduced. Temperatures of up to 1000°C are needed for dopant diffusion in order to form the pn-junction. The HIT cell doped layers are normally formed by PECVD processes below 350°C.
  • The symmetrical structure of the HIT cell also reduces mechanical and thermal stresses. A key factor in enhancing HIT cell performance is the inclusion of the intrinsic amorphous silicon layer. The intrinsic film provides very good passivation of the silicon surface by reducing interface defect density.

Process Development

Fraunhofer ISE has undertaken a comprehensive development program and endeavors to optimize the intrinsic film deposition methodology and processes using a PlasmaPro System100 cluster tool as shown in Figure 2. The system comprises a remote inductively coupled plasma chemical vapour deposition module (ICPCVD), parallel plate plasma enhanced chemical vapour deposition module (PECVD) and sputter process module. Options that include variable height tables and the ability to ramp gas flows and plasma power are present. Process characterisations were done by comparing parallel plate PECVD with ICPCVD depositions in order to achieve the best intrinsic layers. Passivation characteristics were ascertained by measurements of minority carrier lifetime using crystalline silicon substrates.

PlasmaPro System100 installed at FhG ISE

Figure 2. PlasmaPro System100 installed at FhG ISE

A main target is to achieve high carrier lifetime for low intrinsic film thickness of ~5 to 10 nm. Results were also monitored against time as deposited and post annealed samples that in each case, showed time dependent lifetime degradation. This information dictated a strict timing regime for lifetime measurements to enable comparison between processes. Statistical designs of experiment were used to highlight the key parameter or parameter combinations that have a unique effect on carrier lifetime. The results of these experiments are summarized for both ICPCVD and parallel plate PECVD in Figure 3 and Figure 4 respectively.

Relative significance of ICP deposition parameters on lifetime

Figure 3. Relative significance of ICP deposition parameters on lifetime

Relative significance of parallel plate PECVD deposition parameters on lifetime

Figure 4. Relative significance of parallel plate PECVD deposition parameters on lifetime

The PECVD samples also show considerable trend shifts based on whether the samples were measured as deposited or after annealing at 250°C for 10 mins. Optimized intrinsic amorphous silicon processes were developed for both the ICPCVD and parallel plate PECVD modules and these were then compared for passivation quality against film thickness. The results are shown in Figure 5.

Thickness dependence and process comparison of passivated lifetimes

Figure 5. Thickness dependence and process comparison of passivated lifetimes

Summary

By using the PlasmaPro System100, process optimisation of both ICPCVD and parallel plate PECVD confirmed that a good passivation is possible by both methods. Softer or low damage depositions offer superior passivation quality however, for thin intrinsic amorphous silicon layers below 7 nm, the ICPCVD method delivers excellent minority carrier lifetime results. High solar cell efficiencies have also been determined for the two deposition methodologies. Results are quite similar but again, the ICPCVD showed an improvement over the parallel plate PECVD with a cell efficiency of 18.7% as opposed to 8.5%.

This information has been sourced, reviewed and adapted from materials provided by Oxford Instruments Plasma Technology.

For more information on this source, please visit Oxford Instruments Plasma Technology.

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