The two techniques utilized to achieve deep etches in the fabrication of micro-electro-mechanical systems (MEMS) are the Cryogenic and Bosch Process. Due to system and process development over the years there has been a lot of modifications in the methods though the fundamental aspects of each remain the same.
The importance of nanoscale etching has greatly increased and finds usage in nano imprint lithography, storage media etc. MEMS structures range in depth from around 10µm to 500µm with typical openings of more than 1µm. Nanoscale normally refers to structures less than 100nm etched up to several microns deep.
It is difficult to use the Bosch process for this type of structure due to the nature of the etching process, cryo etching lends itself to this feature size. We will also describe an alternative process.
The ‘Bosch’ Process
In this technique, fluorine-based plasma chemistry is used for silicon etching, which is combined with a fluorocarbon plasma process to offer sidewall passivation and enhanced selectivity to masking materials. A complete etch process includes etching and deposition steps several times to attain deep, vertical etch profiles.
The technique depends on breaking down of the source gases in a high-density plasma region before it reaches the wafer, which ensures a small but controlled voltage drop from the plasma.
It is not possible to perform this technique in reactive ion etch systems (RIE), as these have the wrong balance of ions to free radical species. The balance is achievable in high-density plasma systems (HDP).
The most commonly used form of HDP uses inductive coupling to generate the high-density plasma region hence it is known as ‘inductively coupled plasma’ (ICP). The source gas used to provide the fluorine for silicon etching is Sulphur hexafluoride (SF6). This molecule will easily break up in high-density plasma to release the free radical fluorine. The sidewall passivation and mask protection is provided by octofluorocyclobutane (c-C4F8), a cyclic fluorocarbon that disintegrated to produce CF2 and longer chain radicals in the high-density plasma.
These readily deposit as fluorocarbon polymer on the samples being etched. The etch rate, profile, and selectivity to the mask material are all controlled by adjusting the etch step efficiency, the deposition step efficiency or the ratio of times of both the steps.
The basics of a good Bosch etching system are detailed below. There are a number of significant features of the equipment used for Bosch processing that differ from normal ICP systems.
- Quick pumping – To achieve high etch rates, high flows of process gases need to be used at the desired pressure using a large capacity turbomolecular pump along with an appropriate high capacity rotary pump.
- Quick response mass flow controllers.
- Minimum 100 mm separation between the wafer and ICP region. Hence the ratio of ions to free radicals is reduced, as the free radicals have longer decay times than the ions.
- Purely inductive coupling of power in the ICP region, which ensures better uniformity of plasma within the ICP region.
- The walls, lid and pump lines should be heated, which ensures reduction of the deposition of fluorocarbon polymer in regions where it may flake and fall as particles on the wafer. The deposition of sulphur compounds in the pumping line and on the turbo pump is also reduced.
- Short mixed gas line between the mass flow controllers and the process chamber.
- High efficiency wafer cooling to eliminate heat from the wafer generated by the use of higher ICP powers and higher etch rates.
A typical system layout is shown Figure 1:
Figure 1. Oxford Instruments Plasma Technology’s 300mm compatible ICP source
Bosch Process Advances
Certain observations regarding the Bosch Process for MEM’s applications are listed below:
- Initially highest etch rates of silicon were 3-5 µm/min.
- Now it is being claimed that etch of more than 50µm/minute is possible.
- However, the Bosch process uses gas chopping switching between isotropic etches and polymer formation, due to which, etching at these rates usually leaves rough sidewalls.
- High etch rates need very high gas flows of both SF6 and C4F8 and large turbomolecular pumps leading to high costs.
- In order to achieve the majority of device needs, the process requires precise gas control and switching, quick RF matching and fast response pressure control, which are not possible to achieve at higher etch rates.
Figure 2 shows a result from a bulk silicon etch. This process was performed on a 150 mm wafer with patterned resist that etched at a rate of 17 µm/min having a near vertical profile. Etch uniformity across the wafer was ±3%.
Figure 2. 100µm deep etch at 17µm/min
Figure 3. 110 µm deep etch
Figure 3 shows a bulk etch process etched at a slower rate of 10µm per minute with vertical sidewalls.
The control of the gas switching ratios, pressure and power can enable high rate processing up to 10µm/min through wafer etches with smooth sidewalls as shown in figures 4a-c, even at 10:1 or greater aspect ratios.
Figure 4a. Through wafer etch with smooth sidewalls
Figure 4b. Sidewall roughness
Figure 4c. Through wafer etch
Aspect Ratio Dependent Etching (ARDE)
This kind of etching occurs when there is a range of different size trenches on one wafer, which will reach differing depths in a given time. This is clearly seen in Figure 5. Previously, this could only be optimised by etching to a buried oxide layer or SOI layer but now by controlling the deposition cycle of the process, ARDE can either be reduced or eliminated as shown in Figure 6.
Figure 5. Trench depth variation with width.
Figure 6. Control of ARDE
While etching down to a buried oxide layer it is difficult to control the behaviour of the process once it hits the buried layer. In case the process is simply left on to achieve a timed over-etch period, this will cause ‘notching’, as shown in Figure7.
The method used to eliminate this is to actually pulse the platen power at a specified frequency. The charge build up at the SOI interface is reduces and thus the notching at the interface is also reduced as seen in Figure 8. The amount of notching versus duty cycle is shown in figure 9 for a range of trench sizes.
Figure 7. Notching at buried oxide interface
Figure 8. Control of Notching at SOI interface using RF Pulsing SOI notch vs Pulsed LF duty cycle
Figure 9. Graph showing SOI notch control vs. Duty Cycle
Typical Applications of the Bosch process are highlighted below:
In this method also, SF6 is used to provide fluorine radicals for silicon etching. The silicon is removed in the form of SiF4, which is volatile. The major difference is in the mechanism of sidewall passivation and mask protection. Instead of using a fluorocarbon polymer, this process relies on forming a blocking layer of oxide/fluoride (SiOxFy) on the sidewalls (around 10-20nm thick), along with cryogenic temperatures inhibiting attack on this layer by the fluorine radicals.
This can be done in the same equipment as the Bosch process. The various requirements for the equipment are listed below:
- Cryogenically cooled stage. This needs liquid nitrogen cooling to achieve temperatures down to –110°C. The stage must have helium injected behind the wafer to provide good thermal contact. There should not be any seals on or in the stage, as any seal material will loose its flexibility at cryogenic temperatures.
- Low flow mass flow controller (MFC) for oxygen. The shape of etch profile becomes more positive as more oxygen is added. Too much oxygen will cause the formation of black silicon as tiny imperfections in the etching surface act as micromasks.
- Efficient wafer clamping. This is necessary in order to achieve precise temperature control of the wafer surface.
- Least amount of variation in feature dimensions. This is not a machine variable, but is important in setting up processes. Different sizes of features will show different etch characteristics that includes etch depth for a given process/time.
The basic deep processes for the cryo process has not changed over the years the etch rates depending on the aspect ratio are typically greater then 2µm/min a couple of examples below of trench etching carried out at >3µm/min see figure 10 and 11.
The main highlight of the cryo etch is the very smooth sidewalls which can’t be achieved by the Bosch process as well as can render a positive profile, an example is shown in Figure 12.
A recent advance in cryo etching has been the elimination of the notch at the mask/Si interface which is a known issue with the process. This has been eliminated by the use of both hardware and the ramping of gas ratios during the primary stages of the process, the results are shown in figures 13 and 14.
Figure 13. Notch at mask/Si interface
Figure 14. Elimination of notch
A typical application of the cryo deep process is highlighted below, the smooth sidewalls make it very applicable for moulds, optical devices etc.
Cryo etching normally operates at a lower bias level (typically 15-20 V) when compared to the Bosch process (around 50 V). This results in minimal attack on the mask material giving higher selectivity. Nanoscale etches also need smooth sidewalls the downside of the traditional Bosch etch is that since etching and passivation steps are discrete, the sidewalls will develop scalloping or a bit of isotropic etching.
We will compare cryo etching here with a couple of other techniques used for nanoscale etching. Photonic crystals need controlled etching of the silicon with smooth sidewalls. Figure15 shows a typical mask with 200nm openings, Figure 16 shows the result of the etch under cryo conditions to a depth of greater than 1.6µm at an etch rate of 0.5µm/min
Figure 15. Mask pre-etch
Figure 16. Photonic crystal post etch
Figures 17 and 18 show further applications of the cryo process to nanoscale etching, in Fig. 17 we have 50nm lines and spaces etched over 500nm deep with the mask still intact, in Figure 18 we have 300nm trenches etched 15µm deep into silicon which is an aspect ratio of 50:1.
Figure 17. 50nm features etched >500nm deep
Figure 18. 300nm features etched >15µm deep (AR 50:1)
Other process techniques that can be used for nanoscale etching are gas mixing, which uses SF6 mixed in the same step with C4F8, this is sometimes called Pseudo Bosch process and HBr based process chemistry. The etch rates can be controlled to some extent by changing the gas ratios but it is not as controllable as with the cryo process, an example is shown in Figure 19.
Figure 19. Mixed SF6/C4F8
HBr process chemistry is very selective to silicon dioxide, but etch rates are slower then the cryo and the gas chemistry is not as clean as the other nanoscale techniques leading to greater chamber cleans, an example of a HBR etch stopping on a 3nm SOI layer is shown in Figure 20.
Figure 20. HBr etch Courtesy of AMO Aachen
Both the Bosch and Cryo techniques discussed have evolved over the years both in terms of hardware and process. The Bosch process offers higher etch rates but at the cost of sidewall roughness. To limit this roughness the rates are usually in the range of 10-20µm, which is still higher then the cryo process.
To achieve the ultra high etch rates claimed for the Bosch process means very high flows of gas and requires very big turbomolecular pumps, which result in a higher costs. The Bosch process also does not offer very good positive profiles, which the cryo can. The cryo process has also found a growing market in the etching of Nanostructures as the Bosch process leaves scallops in the walls, which in most case is undesirable for the application.
Both the Bosch and Cryo processes will find applications in the advancing field of integrated sensors and actuators, but cryo has distinct advantages in the nanoscale arena. In the end, the user must decide which process will be most appropriate for their application.
This information has been sourced, reviewed and adapted from materials provided by Oxford Instruments Plasma Technology.
For more information on this source, please visit Oxford Instruments Plasma Technology.