Posted in | Materials Research

Progress in GaN-on-Silicon Technology Paves Way for Scalable High Electron Mobility Transistors

This is a GaN on 200 mm Si wafer thickness mapping image. (Credit: University of Illinois)

Researchers at the University of Illinois have advanced gallium nitride (GaN)-on-silicon transistor technology recently by optimizing the composition of the semiconductor layers that constitute the device. The team in partnership with Veeco and IBM developed the high electron mobility transistor (HEMT) structure on a 200 mm silicon substrate with a process that can be scaled to larger industry-standard wafer sizes.

According to Electrical and Computer Engineering Assistant Professor Can Bayram, his team developed the GaN HEMT structure on a silicon platform as it is well-suited with current CMOS manufacturing processes, and compared to other substrate options like silicon carbide and sapphire, it is less expensive.

However, silicon does have certain challenges, for instance the lattice constant, or space between silicon atoms, does not match up with the GaN’s atomic structure grown on top of it.

When you grow the GaN on top, there’s a lot of strain between the layers, so we grew buffer layers [between the silicon and GaN] to help change the lattice constant into the proper size.

Josh Perozek, ECE Undergraduate

Without these buffer layers, cracks or other defects will develop in the GaN material, which would prevent the transistor from functioning accurately. Specifically, these defects - holes or threading dislocations where atoms should be - destroy the properties of the 2D electron gas channel in the device. This channel is vital to the HEMTs ability to conduct current and operate at high frequencies.

“The single most important thing for these GaN [HEMT] devices is to have high 2D electron gas concentration,” said Bayram, about the buildup of electrons in a channel at the interface between the silicon and the assortment of GaN-based layers above it.

The problem is you have to control the strain balance among all those layers - from substrate all the way up to the channel - so as to maximize the density of the of the conducting electrons in order to get the fastest transistor with the highest possible power density.

Can Bayram, Assistant Professor, University of Illinois

After analyzing three different buffer layer configurations, Bayram’s team realized that thicker buffer layers composed of graded AlGaN minimize threading dislocation, and stacking those layers decreases stress. The team were able to achieve an electron mobility of 1,800 cm2/V-sec, with this type of configuration.

“The less strain there is on the GaN layer, the higher the mobility will be, which ultimately corresponds to higher transistor operating frequencies,” said Hsuan-Ping Lee, an ECE graduate student researcher leading the scaling of these devices for 5G applications.

The subsequent step for his team, according to Bayram, is to fabricate fully functional high-frequency GaN HEMTs on a silicon platform, which can be used in the 5G wireless data networks.

When it is fully deployed, the 5G network will enable swifter data rates for the eight billion mobile phones worldwide, and will offer better performance and connectivity for driverless cars and Internet of Things (IoT) devices.

The team, in partnership with IBM and Veeco, conducted their research at the Micro + Nanotechnology Lab with support from the Air Force Office of Scientific Research.

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