Wireless consumer devices such as tablet PCs, smart phones and e-book readers are ever increasing in popularity and there are continual demands for further enhancements. Over the years, the performance of ICs has also significantly improved, however technology for packaging circuits is not up to the mark.
Recently, a new technology known as Quilt Packaging (QP) has evolved, which holds high promise for lowering cost and boosting system-level IC package performance. Professor Gary H. Bernstein, Department of Electrical Engineering, Center for Nano Science and Technology, at the University of Notre Dame, developed a 2D system-in-package paradigm together with his graduate student, Quanling Zheng and others. This solution was developed for highly efficient chip-to-chip interconnection.
Bandwidth and heat removal is increased using QP technology thus ensuring better performance and cost-effectiveness.
An Olympus LEXT OLS4000® laser scanning confocal microscope was chosen by the team to support the development process, providing information to help the lab staff, fine-tune the fabrication process and provide accurate and repeatable measurements. Since researchers required 3D imaging, the OLS4000 was selected over the lab’s SEM and it was chosen instead of the stylus profilometer as it offers quicker 3D and roughness measurements.
In addition, it is possible to measure critical steep profiles down to the bottom of a trench with this instrument, while on the other hand, a stylus tip is not able to touch the bottom as it collides with the sidewall. The OLS4000 offers excellent imaging resolution by using a short wavelength laser.
How Quilt Packaging Works
QP is based on established MEMS-inspired fabrication techniques and is both practical and simple. In this method, ICs can be tiled in two dimensions with gaps of just a few microns between each pair of chips by rendering contiguous chip-to-chip interconnections. The sides of each chip have short conductive nodules which horizontally protrude in order to link directly to matching nodules on other ICs. This interconnected chip array is known as a quilt.
The benefits of QP are:
- Weight and power dissipation
- Reduced cost
- Heterogeneous integration
- High input/output density
- High bandwidth with no more than 0.1dB insertion loss caused by nodules up to 110 GHz
- Compatibility with current packaging technology and cooling schemes
As seen in Figures 1 to 3, I/O structures ranging from 10 pm to 100 pm wide have been fabricated at Notre Dame.
Figure 1. Rendering of QP interconnection, showing the edge nodules deposited deep into the substrate.
Figure 2. One pair of assembled chips showing coplanar waveguides connecting them.
Figure 3. Quilt-packaged chips held on edge by tweezers, supported by the interconnected nodules.
Measuring Etch Depth
In QP there are a few additional steps when compared to traditional IC manufacture. Firstly, etching the nodule trench is done with silicon as the substrate at Notre Dame. By performing 5mins deep reactive Ion Etching (DRIE), 20µm deep trenches are obtained. The step profile of the nodule trench is measured easily, quickly and precisely with the OLS4000 as seen in Figure 4.
Measuring Surface Roughness
After the nodule trench is etched, electroplating of copper is done to fill the trench and the overburden is removed with chemical-mechanical polishing (CMP). After the polishing is finished, the abrasive particles, typically sub-micron silica or alumina in the polishing slurry, can adhere to the wafer surface and cause contamination. As shown in Figures 5a, 5b and Table 1, the OLS4000 offers a quick and accurate method to measure surface roughness, taking less than 1min to perform measurements that help to ensure that the final product performs as expected.
Figure 4. Step profile measurement for nodule trench etch step.
Figure 5. Surface roughness measurements just after the CMP process. At (a), surface area texture measurement result just after the CMP process. At (b), the same measurement result after post-CMP cleaning.
Table 1. Laser confocal microscope data provides a comparison of surface roughness parameters before and after post-CMP cleaning.
|Surface Roughness Parameters
||Before Post-CMP Cleaning
||After Post-CMP Cleaning
|Arithmetic Average Roughness Ra
|Peak-to-Valley Roughness Rz
|Root Mean Square Roughness Rq
Measuring the Vertical Offset
The dry etching of chips are performed for separation after cleaning and then assembly is carried out as shown in Figure 6. Problems may arise if there is too much vertical offset between two chips' nodules.
The electrical performance of the package is impacted by extreme changes in contact area. As a result, care must be taken to monitor any vertical offsets between the nodules of various chips. It is possible to obtain surface morphology and vertical offset information with the OLS4000 microscope in order to make sure that each "tile" is correctly aligned.
Figure 6. 2D image of assembled chips.
Speed and Accuracy
The OLS4000 is used at different stages as it not only offers 3D measuring capabilities and precise surface roughness measurements, but because both types of data can be collected much more quickly than with other instruments, as the microscope captures images and performs measurements in seconds, where stylus-based systems require a probe to travel across a surface, which is much slower.
The other advantages of the microscope are highly precise color imaging as well as its ease of use and convenience. The other instruments require extensive training but the Olympus system is very easy to learn how to use. The research team is presently working on developing methods in order to expand its utility and performance and make it more cost-effective to implement on a larger scale.
Indiana Integrated Circuits, a new startup is commercializing QP technology for MEMS integration, RF systems, high performance computing and other applications.
With IC manufacturing and packaging in very high demand, Dr. Bernstein's laboratory has developed a chip-to-chip interconnect technique known as Quilt Packaging, in which small metal nodules protruding from the edges of chips help them to communicate with ultra-wide bandwidth and low power. This research has resulted in world-record interconnect bandwidth, with below 0.1dB of insertion loss from 50MHz to 100GHz. The team is presently working towards developing an extensive range of commercial applications.
This information has been sourced, reviewed and adapted from materials provided by Olympus Corporation of the Americas Scientific Solutions Group.
For more information on this source, please visit Olympus Corporation of the Americas Scientific Solutions Group.