Certain applications in 3D sensing of VCSEL technology require higher power operation than Data Communication applications. As a result, there is a drive to produce high power VCSEL arrays of varying size and density depending on the combined output power required. However, multiple challenges such as cost control and thermal crosstalk between VCSELs arise when producing high power arrays. In addition, challenges also occur in the process of fabrication of VCSELs. As the density of the arrays increase, better process control becomes critical to deliver performance and cost.
Discussion on the Impact of Dry Etching on Demonstrating Reliable Performance at Low Cost
Dry etching of the VCSEL mesa is one of the critical steps within the process of fabrication of VCSEL. The mesa structure confines the light and exposes the high Al content layers for the oxidation process afterward. The mesa structure is formed by etching the top DBR stack. During this process, the control of the diameter of the mesa is important to define the size of the apertures. The sidewalls also have to be clean and smooth to prevent non uniformity of the aperture. In addition, it is critical to control the end layer across the full wafer size.
The end layer affects the electro optical performance, the yield and the reliability of the device.
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This information has been sourced, reviewed and adapted from materials provided by Oxford Instruments Plasma Technology.
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