Atomic Layer Deposition and Atomic Layer Etching for GaN Power Electronics

New GaN power electronics are being developed for power conversion and delivery. In electric transportation such as Electric and Hybrid Electric Vehicles (EV and HEV), these devices are becoming increasingly important and device cost and efficiencies are critical for their success. The high mobility and breakdown voltage of GaN make it an ideal material for power devices. In particular, the 2D electron gas occurring at the AlGaN/GaN interfaces allows for very effective devices. However, the AlGaN layer requires a negative voltage on the gate to turn off. Such “D-mode” or “normally-on” devices do not meet fail-safe design criteria and therefore there is a strong drive to develop “E-mode” or “normally-off” devices. There are several strategies to create such devices and using recess etching of the AlGaN barrier is a prominent one. Furthermore, gate dielectric layers are desired to limit leakage currents.

E-mode GaN-on-silicon power device. Using a recess etch and a gate dielectric can allow for a normally-off device with low leakage and low power losses. Atomic Scale processing techniques such as ALD and ALE are needed to control etch and deposition and have low damage to the sensitive interfaces.

Figure 1. E-mode GaN-on-silicon power device. Using a recess etch and a gate dielectric can allow for a normally-off device with low leakage and low power losses. Atomic Scale processing techniques such as ALD and ALE are needed to control etch and deposition and have low damage to the sensitive interfaces.

A cross-sectional schematic of an E-mode GaN-on-silicon power device is shown in Fig. 1. Note that various designs have various depths of recess etches, ranging from almost no recess to complete removal of the AlGaN barrier layers and even partly the GaN channel. In all of these cases, a high-quality dielectric and high-quality interface with the dielectric are desired to allow for an E-mode device with low leakage and low power losses. In contrast to other semiconductors, the GaN surface is one of the most process-sensitive in the electronic industry 1. Therefore, precise control of the applied processes is needed. Several challenges exist around recess etching and gate dielectric deposition which will be discussed further. For the recess etch, the AlGaN layer needs to be etched down to the underlying GaN. This AlGaN layer is thin, typically 20-30 nm and there is no inherent selectivity to GaN for a classic etch process. Therefore, an extremely uniform, reproducible, and slow etch rate is essential to have a satisfactory etch result across a complete 200 mm wafer. For the dielectric deposition, a thin conformal dielectric must be deposited in the recess structure. For both the etch and the deposition the processes should have low damage and result in high-quality interfaces with low defect levels. Plasma processes are desirable here to allow for directional etching and to help deposit high-quality layers at modest thermal budget. The reactive species in the plasma such as radicals and ions mean that etching is facile and high-quality material can be deposited as well. However, it also means that the energy and fluxes of the species must be carefully managed to limit damage to the device.

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