Aug 5 2014
Cadence Design Systems, Inc., a leader in global electronic design innovation, today introduced Cadence® Voltus™-Fi Custom Power Integrity Solution, a transistor-level electromigration and IR-drop (EMIR) solution that delivers foundry-certified SPICE-level accuracy in power signoff to create the fastest path to design closure.
The new solution is enabled by Cadence Spectre® Accelerated Parallel Simulator signoff SPICE simulation, providing best-in-class accuracy at the transistor level to meet complex manufacturing specifications at advanced nodes. It complements Cadence Voltus IC Power Integrity Solution, a full-chip, cell-level power signoff tool, and completes the company’s power signoff technology solution.
Highlights:
- Provides best-in-class transistor-level EMIR accuracy, enabled by Spectre Accelerated Parallel Simulator SPICE simulation
- Voltus-Fi Custom Power Integrity Solution completes Cadence power signoff solution
- Delivers best-in-class accuracy for advanced node FinFET process
Voltus-Fi Custom Power Integrity Solution enables designers to shrink the critical power signoff closure and analysis phase through key capabilities including:
- Cadence’s patented voltage-based iteration method, which requires a smaller memory footprint and runs faster than the industry’s traditional current-based iteration method
- Full integration with the Cadence Virtuoso® platform, which provides a single design flow that improves designer productivity in analog and custom block EMIR signoff
- Leverages transistor-level parasitic extraction with Cadence Quantus™ QRC Extraction Solution, transistor-level simulation with Cadence Spectre Accelerated Parallel Simulator and Cadence Spectre Extensive Partitioning Simulator and, finally, EMIR results visualization on real physical layouts for quick analysis, debugging and optimization
- Integration between Voltus-Fi Custom Power Integrity Solution and Voltus IC Power Integrity Solution, which provides a seamless flow for advanced analog/ mixed-signal power signoff for designs with mixed transistor-level and cell-level blocks
“The lowest possible power is imperative to customers of our iCE40 and ECP5 FPGA product families, and Voltus-Fi Custom Power Integrity Solution ensures that we achieve exceptionally accurate transistor-level results while minimizing power consumption,” said Sherif Sweha, corporate VP of research & development at Lattice Semiconductor. “As Lattice continues its focus on mobile and mobile-influenced markets, we are also using Voltus IC Power Integrity solution at the cell-level for a complete, best-in-class power signoff solution that optimizes mobile devices.”
“With the Cadence Voltus-Fi Custom Power Integrity Solution, customers can now achieve the most accurate EMIR results for transistor-level blocks, from analog IP blocks to embedded memories, in their Virtuoso environment,” said Anirudh Devgan, senior vice president, Digital & Signoff Group, Cadence. “In addition, Voltus-Fi Custom Power Integrity Solution generates accurate IP-level power-grid models for transistor blocks. This enables customers to then run Voltus IC Power Integrity Solution to achieve complete, full-chip SoC power signoff at top level, which results in the fastest path to design closure.”
Voltus-Fi Custom Power Integrity Solution is available now. For more information, visit www.cadence.com/news/voltusfi.
Source: http://www.cadence.com/