NASA Use Carbon Nanotubes in Integrated Circuits - News Item

NASA researchers have reported a new method for producing integrated circuits using carbon nanotubes instead of copper for interconnects. This technology may extend the life of the silicon chip industry by 10 years. It may also help sustain Moore’s Law, which states that the number of transistors in a given area if an integrated circuit would double every 18 months.

Carbon nanotube use in integrated circuits has the advantage that they can conduct very high currents, of the order of a million amperes in a square centimetre without deterioration. This is beyond the performance of existing copper interconnects as its resistance to current flow increases with decreasing conductor size.

Furthermore, the use of carbon nanotubes removes the need for creating trenches to bury copper conductors in silicon wafers. This process is becoming increasingly more difficult with component size decreasing.

The process will also allow chip manufacturers to be able to add more layers to silicon chips to increase their computing capabilities. It will also allow them to decrease chip size further and they will no longer be restricted by the limitations of the copper interconnects.

The process itself involves growing the carbon nanotubes on the surface of silicon wafers via a chemical process, followed by the deposition of a silica layer to fill the space between the nanotubes. The surface is then polished flat, after which more layers can be deposited, including vertical carbon nanotube interconnects.

Further details of the process were published in the April 14 issue of the Journal of Applied Physics Letters.

 

Posted April 14th, 2003

 

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