Failure Analysis in Integrated Circuits - Anisotropic Dielectric Removal vs. Sequential Removal

While conducting failure analysis of integrated circuits, it is essential to open and delayer chip layers one by one in order to discover a defect or hidden defects. The reason for failure needs to be determined to ensure that the defect does not occur again and to improve the device’s performance.

Delayering of the Integrated Circuit

Based on the desired information, delayering of the integrated circuit is performed using one of the following two strategies::

  • Anisotropic removal of all dielectric layers
  • Sequential removal of all layers including conductors

These strategies are described in more detail in the following sections.

Skeleton Etch or Anisotropic Removal of Dielectric Layers

This method involves anisotropic removal of all dielectric layers down to the silicon surface. As shown in Figure 1, metal conductors will remain atop dielectric material pedestals. It is important to use an anisotropic etch for prevention of undercut of the metal lines or the metallic stress will cause delamination. When the silicon dioxide etch approaches the polysilicon gate material, a CF4 + CHF3 gas mix is utilized to enhance selectivity to silicon and minimize erosion of the polysilicon lines.

“Skeleton” etch sequential removal

Figure 1. “Skeleton” etch sequential removal

Sequential Removal

Anisotropic dielectric removal is beneficial, but in many cases defects or other features of interest may be present below the conductors. In such cases, sequential removal of metal and dielectric layers is desired.

One may feel that by just reversing the etch processes utilized for circuit fabrication, delayering of the circuit is possible. But it is essential to note that when reactive ion etching is performed during fabrication, photoresist is present on the surface of the circuit in order to cover regions that do not require etching. Each etch step ends at an “etch stop”, which is a layer having a minimal etch rate for the etch. But when sequential etching is done, none of these are true. Appropriate etch recipe selection is critical to prevent unintended removal of layers that need not be etched. When the upper metal level is etched, lower level metal should not be exposed or the lower level metal layers will be removed prematurely.

Oxide Sidewalls

Since interlayer dielectrics are normally quite planar, theoretically a planar surface can be maintained during alternate delayering of dielectric layers and metal lines. The uppermost dielectric layer also termed as the passivation is not normally planarized. Since this silicon nitride or silicon oxide layer is conformal, anisotropic RIE removal results in an “oxide sidewall” surrounding the metal line. The sidewall may also have a sidewall polymer and the aluminum native oxide formed during IC fabrication both of which are highly plasma etching-resistant. It is not easy to remove the sidewall features by RIE and simply move downward while performing an anisotropic etch. The oxygen sidewalls may be removed using a dilute PSG etch or buffered HF solution. Addition of a higher oxygen content can also help in minimizing or solving this problem.

Planar Delayering

In order to ensure planarity while conducting sequential IC delayering, it is preferred that each dielectric etch is stopped when a specific level is attained, which is uniform with the next metal layer that needs to be etched. Hence while etching the passivation, it is necessary to etch it level with the metal line base. This process requires a timed etch because there is no etch stop between the dielectric layers. The time determination is done using trial and error for any particular integrated circuit process utilizing a number of test pieces for process development. If the etch process is not timed properly, a metal line is created either atop an oxide pedestal or inside a trough. On removal of this metal line, this trough or pedestal geometry will be moved downward towards the next oxide etch step as the oxide is an anisotropic one. In case delayering is not performed in a planar manner, more and more topography will be formed making the surface highly irregular. In case the goal is to remove all dielectric and metal layers so that polysilicon defects can be clearly seen, the simplest way is to dip the component in dilute hydrofluoric acid (HF). All dielectric materials will be isotropically etched by HF and will cause undercutting of metal lines resulting in removal of all conductors except polysilicon.

This information has been sourced, reviewed and adapted from materials provided by Trion Technology.

For more information on this source, please visit Trion Technology.

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