Nov 20 2013
Cadence Design Systems, Inc., a leader in global electronic design automation, today announced that Faraday Technology Corp., based in Hsinchu, Taiwan, deployed a full Cadence® tool flow to create its largest System-on-Chip (SoC), a 300-million-gate design for a 4G base station. By using Cadence Encounter® digital design tools in Faraday’s hierarchical flow, the design team completed this complex SoC, from data-in to tapeout, in just seven months.
Faraday successfully reduced the time for each prototyping run of this SoC design from two weeks to 3-5 days by leveraging the Encounter Digital Implementation (EDI) System, including GigaOpt multithreaded optimization and advanced analysis, Encounter Conformal® Equivalence Checker (EC) for hierarchical EC compare methodology, and integrated signoff tools for RC extraction and timing analysis.
Additional Cadence products used include Incisive® Enterprise Simulator, Verification Intellectual Property (VIP), Encounter Power System, Allegro® Package Designer and Allegro Sigrity™ signal and power integrity solutions.
“This SoC was the biggest project we’ve undertaken, and is the most complex one ever in Taiwan, so we compiled the best tool set we could to ensure success—in performance, quality and in time to market,” said Jason Hung, RD vice president of Faraday. “Cadence’s wide array of digital implementation and verification products plus the level of support we received helped us achieve all our goals.”
For more information about this project, click here. Faraday plans to discuss this project at Embedded Technology 2013 Conference and Exhibition in Yokohama, Japan, Nov. 20-22.
Source: http://www.cadence.com