Development of Ultra Low-k Material and Interconnect Process for Next Generation Memory Devices
Hitachi, Ltd. and Hitachi Chemical Co., Ltd. have announced that they have developed an ultra low dielectric constant spin-on glass (ultra low-k SOG) with a dielectric constant of k=2.4 and an interconnect (wiring) process, required for sub-50nm memory device fabrication. As a result of these developments, the mechanical strength of the low-k SOG was doubled in comparison to conventional SOGs; thermal stability was greatly increased to 800°C, and the interconnect process was simplified. These developments will contribute to both increasing the performance, as well as decreasing the costs of next-generation memory devices.
Memory devices, such as flash memories and dynamic random access memories (DRAMs), have rapidly increased their storage capacity and cost effectiveness by decreasing critical dimensions. A trade-off in this miniaturization is the increase in parasitic capacitance between memory cells or interconnects, which results in signal delay and high power consumption. Thus, low-k interlayer dielectric films which reduce this parasitic capacitance are considered indispensable in next-generation memory devices with minimum dimensions below 50nm. In general however, simply reducing the dielectric constant leads to decreases in film strength and thermal stability, and gives rise to the need for complicated and expensive processes to overcome these drawbacks. Hitachi and Hitachi Chemical have been involved in the development of low-k SOG (k=2.9) and related processes, however in order to achieve the ”ultra” low-k film required in next-generation memory devices, it was considered necessary to approach the issue from both the material and process perspective.
In response to this challenge, Hitachi and Hitachi Chemical have jointly developed a new SOG which provides a low-k film with high mechanical strength and thermal stability, as well as a low-cost interconnect process, for sub-50nm memory devices. Features of the technology are as follows:
(1) SOG with high planarity, thermal stability and mechanical strength
Interlayer dielectric film in memory devices are required to have high planarity for managing the overall planarity of the hierarchical structure of the devices. To obtain this high planarity, a SOG type insulating material is widely used, where the liquid material is coated on the uneven surface of the substrate to planarize the gaps and thermally cured to provide a hard solid film. While a planar surface is obtained just after coating, the thermal cure causes significant material shrinkage, leading again to an uneven surface. Therefore, a ”re-flowable” SOG is commonly used as its flexible molecular structure allows the material to re-flow to re-planarize during thermal cure. The flexible molecular structure, however, reduces the thermal stability and the mechanical strength of the film. To overcome these issues, a new ultra low-k SOG with suppressed shrinkage and a rigid molecular structure has been developed. Features of the new SOG are a low dielectric constant of k=2.4, high planarity, double the mechanical strength of conventional SOG, high thermal stability of up to 800°C, and high chemical stability, as well. The new SOG can be used not only as an interlayer dielectric between interconnects but also between memory cells which require a high temperature fabrication process.
(2) Simplification of the interconnect process
In the conventional interconnect process, photo-lithography and dry etching are used create via-holes in the interlayer dielectric film to connect the wires, after which the photo-resist layer is removed using an oxygen plasma ashing and wet cleaning. By optimizing the etching condition to create via-holes and also taking advantage of the high chemical stability of the new ultra low-k SOG film a new process was developed which requires only an amine solution to remove the photo-resist. With this method, degradation of the SOG film which occurs during oxygen plasma ashing is avoided, increasing the reliability of the wiring. Further, as the process steps are reduced without the need for new equipment or chemicals, the overall cost of the interconnect process is reduced. The effectiveness of this method has been verified in interconnect prototypes for the 50nm generation.
Posted 27th June 2006