Posted in | News | Ceramic Materials

Pre-Production Availability of Smart Cut Engineered Substrates for GaN Power Decices from Picogiga

Picogiga International, a division of the Soitec Group (Euronext, Paris) announced pre-production availability of SopSiC, a Smart Cut™ engineered substrate for GaN-based power devices. Silicon-on-polysilicon-carbide (SopSiC) bridges the compound epiwafer void between low-cost, low-power gallium nitride (GaN) on silicon and high-cost, high-power SiC for GaN HEMT devices. As such, SopSiC is designed to provide cost-efficient substrate solutions for advanced high-power devices used in wireless (RF) communication systems such as radar, satellite communications and base stations.

“SopSiC is an excellent example of how Smart Cut engineered substrates can be used to solve challenges for III-V applications,” notes Jean-Luc Ledys, COO of Picogiga. “While GaN on both silicon and silicon carbide is part of our existing epiwafer product line for high-power applications, SopSiC gives our customers a significantly better performing solution than silicon - and a considerably less expensive solution than SiC. In terms of dollar/watt, SopSiC is an extremely attractive solution.”

The European HYPHEN (see release dated November 8, 2006) project recently announced excellent initial material characterization results of GaN on SopSiC.

The SopSiC structure, which is engineered using Smart Cut layer transfer and bonding technology, includes: a bottom layer of polysilicon-carbide, an insulating buried oxide layer, and a high resistivity (1-1-1) silicon top layer. The top layer serves as the seed layer for GaN epitaxial growth, which is accomplished using MBE (molecular beam epitaxy) or MOCVD technology. The bottom polysilicon-carbide layer is designed to evacuate the heat generated by high-power HEMT devices. SopSiC marks the first industrialized compound epiwafer product combining both Smart Cut and MBE technologies.

Samples for customers are now available in 3” and 4” diameters. Because the fabrication process is not limited by the small diameters of bulk SiC, the process is scalable to the larger wafer sizes standard for silicon - a 6” version is currently in development.

Tell Us What You Think

Do you have a review, update or anything you would like to add to this news story?

Leave your feedback
Your comment type
Submit

While we only use edited and approved content for Azthena answers, it may on occasions provide incorrect responses. Please confirm any data provided with the related suppliers or authors. We do not provide medical advice, if you search for medical information you must always consult a medical professional before acting on any information provided.

Your questions, but not your email details will be shared with OpenAI and retained for 30 days in accordance with their privacy principles.

Please do not ask questions that use sensitive or confidential information.

Read the full Terms & Conditions.