The University of Tokyo’s Institute of Industrial Science used a ferroelectric gate insulator and an atomic-layer-deposited oxide semiconductor channel to construct three-dimensional vertically structured field-effect transistors for high-density data storage devices.
Furthermore, researchers discovered that by employing antiferroelectric rather than ferroelectric, they were able to erase data with only a small net charge, resulting in more efficient write operations. This research could lead to new data storage memory that is even smaller and more environmentally friendly.
In terms of data storage, consumer flash drives already outperform prior computer media formats in terms of size, capacity, and affordability, but new machine learning and Big Data applications continue to fuel the need for advancement.
Furthermore, upcoming Internet of Things nodes and mobile cloud-enabled devices will demand memory that is both energy-efficient and compact. However, modern flash memory technologies require rather significant currents to read or write information.
The University of Tokyo has now produced a proof-of-concept 3D stacked memory cell based on ferroelectric and antiferroelectric field-effect transistors (FETs) with an atomic-layer-deposited oxide semiconductor channel. These FETs can hold ones and zeros in a non-volatile way, which means they do not need power all of the time.
The vertical device structure boosts data density while lowering operating energy requirements. In a vertical trench structure, hafnium oxide and indium oxide layers were formed. Electric dipoles in ferroelectric materials are most robust when oriented in the same direction. The vertical alignment of the dipoles is naturally enabled by ferroelectric Hafnium Oxide.
The degree of polarisation in the ferroelectric layer stores data, which can be read by the system due to changes in electrical resistance. In the wiped state, antiferroelectrics, on the other side, prefer to shift the dipoles up and down, allowing for effective erasure processes within the oxide semiconductor channel.
We showed that our device was stable for at least 1,000 cycles.
Zhuo Li, Study First Author, University of Tokyo
The researchers experimented with different indium oxide layer thicknesses. They discovered that tweaking this parameter can result in major performance gains. The scientists also plotted the most persistent surface states using first-principles computer simulations.
Our approach has the potential to greatly improve the field of non-volatile memory.
Masaharu Kobayashi, Study Senior Author, University of Tokyo
This sort of research, which combines experimental prototypes with computer models, could pave the way for future consumer devices.
The work is available in the 2022 IEEE Silicon Nanoelectronics Workshop as “A Vertical Channel Ferroelectric/Anti-Ferroelectric FET with ALD InOx and Field-Induced Polar-Axis Alignment for 3D High-Density Memory.”
The JST Intellectual Property Utilization Support Program, Super-Highway, Japan, provided funding for this project.