Feb 6 2013
eSilicon Corporation, the largest independent semiconductor design and manufacturing services provider, today announced that An ASIC Low-Power Primer is now available from Springer, a leading publisher of science and technology reference books. Written by eSilicon engineers Dr. J. Bhasker, architect, and Dr. Rakesh Chadha, director of design technology, the book provides an invaluable primer on the techniques utilized in the design of low-power digital semiconductor devices.
"System power management is a critical aspect of IC design -- everyone cares about low-power design in order to be green; it is no longer the domain of mobile applications. Power management spans technology, standard cell library and memory selection, IP design, RTL design and physical implementation," said Dr. Prasad Subramaniam, eSilicon's vice president of design technology. "This book covers all these topics. And it would be difficult to find a better source than eSilicon and Rakesh and Bhasker who have extensive experience with power management and low-power IC design over multiple generations of technologies. This book reflects the expertise and experience of two of our finest engineering team members and demonstrates the quality of talent we apply to customers' projects every day."
The authors guide readers through architectural and implementation techniques, system power consumption analysis, low power design techniques and more. The duo also wrote Static Timing Analysis for Nanometer Designs: A Practical Approach.
About the Authors
J. Bhasker is an expert in the area of hardware description languages and RTL synthesis. Prior to joining eSilicon, he was a distinguished member of the technical staff at Bell Laboratories. He has published a number of books and papers, primarily in the area of design automation and high-level synthesis algorithms. He was awarded the IEEE Computer Society Outstanding Contribution Award in 2005. He holds a Ph.D. in Computer Science from the University of Minnesota.
Rakesh Chadha is an ASIC design specialist with over 25 years of experience in timing and signal integrity at Bell Laboratories, Cadence and eSilicon. He was responsible for the timing and signal integrity for the Sematech project on Chip Parasitic Extraction and Signal Integrity Verification. He has been responsible for complex SOC design methodology for several generations of process technologies. He holds a Ph.D. in Electrical Engineering from the Indian Institute of Technology Kanpur.
Source: http://www.esilicon.com