SuVolta, Inc., a developer of scalable semiconductor technologies for low-power, high-performance IC chips, today announced that it has realized significant processor speed gains with associated power reduction in an ARM Cortex-M0 processor built using transistor technology from SuVolta.
The ARM Cortex-M series processor was manufactured with SuVolta’s Deeply Depleted Channel™ (DDC) technology on a 65nm bulk planar CMOS DDC process. With SuVolta’s transistor technology, designers are able to significantly reduce power or dramatically improve performance, depending upon design requirements.
“ARM’s heritage is based on low power, so technologies that can further improve power consumption, such as DDC technology from SuVolta, will always be welcomed by ARM and our Partners,” said Noel Hurley, vice president, Strategy and Marketing, Processor Division, ARM. “SuVolta has shown that the DDC technology, when incorporated into an ARM processor, can provide additional power reductions or a significant performance boost. As the Internet of Things continues to expand, innovative ultra-low power technology for sensors and other devices will be vital to ensure that ARM remains at the forefront of this opportunity.”
When compared to an identical ARM Cortex-M0 processor manufactured in the conventional 65nm process, with a 1.2V supply voltage, the DDC transistor-based ARM implementation operating at 0.9V demonstrates the following benefits:
- 50 percent lower total power consumption at matched 350MHz operating speed.
- 35 percent increased operating speed (performance) at matched power.
- 55 percent increased operating speed when operated at matched supply voltage.
“We’ve now validated the benefits of the DDC technology in a complex SoC, by combining the ARM Cortex-M0 CPUs with SRAM instances and various analog components,” explained David Kidd, senior director, digital design at SuVolta. “The results speak for themselves – power-performance optimized CPU cores, with results that hold across process corners and temperature, plus, SRAMs with 150mV lower minimum operating voltage, 50 percent less leakage power at matched SRAM read current, and more than 5x less leakage power in retention mode.”
“Reducing power consumption and enhancing performance are key to providing next-generation capabilities for a variety of advanced digital products,” said Bruce McWilliams, president and CEO at SuVolta. “By validating the speed-power advantages of the DDC technology in a SoC that includes ARM processors, we’ve reached another significant milestone in demonstrating the value of our technology in a system.”
“We continue to make steady progress validating our technology at the advanced nodes by working with top-tier fabless semiconductor companies and foundries,” continued McWilliams.