Finding the optimum answer from a limited number of options is the goal of combinatorial optimization issues, which are the focus of annealing processor design. Practical applications in logistics, resource allocation, and material and drug development are all affected by this. Regarding CMOS (semiconductor technology), annealing processor components must be completely "coupled." However, the scalability of the processors is directly impacted by the coupling's intricacy.
(a) The die photo of a 22nm fully-coupled Ising LSI chip; (b) the front and back views of the board of a 4096-spin scalable full-coupled Ising LSI system. Image Credit: Takayuki Kawahara from TUS
Under the direction of Tokyo University of Science Professor Takayuki Kawahara, researchers have created and successfully tested a scalable processor that divides the calculation among many LSI chips in a new IEEE Access study that was published on January 30, 2024. On January 25th, 2024, the innovation was again presented at the 22nd IEEE World Symposium on Applied Machine Intelligence and Informatics (SAMI 2024).
We want to achieve advanced information processing directly at the edge, rather than in the cloud, or performing preprocessing at the edge for the cloud. Using the unique processing architecture announced by the Tokyo University of Science in 2020, we have realized a fully coupled LSI (Large Scale Integration) on one chip using 28nm CMOS technology. Furthermore, we devised a scalable method with parallel-operating chips, and demonstrated its feasibility using FPGAs (Field-Programmable Gate Arrays) in 2022.
Takayuki Kawahara, Professor, Tokyo University of Science
The researchers developed a scalable annealing processor in the study, partially funded by the Tokyo Metropolitan Government, the Tokyo University of Science Entrepreneurship Grant (PoC Support Grant), and the JSPS KAKENHI Grant Number 22H01559.
One control FPGA and 36 22 nm CMOS calculating LSI (Large Scale Integration) chips were employed. With the aid of this technique, large-scale fully coupled semiconductor systems with 4096 spins that adhere to the Ising model—a mathematical representation of magnetic systems—can be built.
The Tokyo University of Science created two different technologies combined in the processor. This includes a methodology that cuts the amount of chips needed in half compared to traditional approaches and a “spin thread method” that allows for eight parallel solution searches.
Its power requirements are very low; it uses 2.9W of electricity (1.3W for the core part) while operating at 10 MHz. Using a 4096-vertice vertex cover issue, this was practically confirmed.
The processor performed 2,306 times better in power performance ratio than replicating a fully coupled Ising system on a PC (i7, 3.6GHz) using annealing emulation. It also outperformed the arithmetic chip and core CPU by a factor of 2,186.
This processor’s successful machine verification raises the prospect of enhanced capacity.
Kawahara added, “In the future, we will develop this technology for a joint research effort targeting an LSI system with the computing power of a 2050-level quantum computer for solving combinatorial optimization problems. The goal is to achieve this without the need for air conditioning, large equipment, or cloud infrastructure, using current semiconductor processes. Specifically, we would like to achieve 2M (million) spins by 2030 and explore the creation of new digital industries using this.”
In conclusion, scientists have created a fully coupled, scalable annealing processor that can accommodate 4096 spins on a single board comprising 36 CMOS chips. This advancement was significantly helped by significant advances such as chip reduction and parallel operations for simultaneous solution searches.
Journal References:
Megumi, T., et. al. (2024) Scalable Fully-Coupled Annealing Processing System Implementing 4096 Spins Using 22nm CMOS LSI. IEEE. doi:10.1109/ACCESS.2024.3360034
Endo, A., et. al. (2024) Fabrication and Evaluation of a 22nm 512 Spin Fully Coupled Annealing Processor for a 4k Spin Scalable Fully Coupled Annealing Processing System. IEEE. doi:10.1109/SAMI60510.2024.10432908
Source: https://www.tus.ac.jp/en/