As transistors approach atomic dimensions, the interface between different materials grows in importance. Researchers from?National Yang Ming Chiao Tung University (NYCU), TSMC Corporate Research, and colleagues from National Taiwan University, Academia Sinica, and the National Center for Instrumentation Research have devised an interface engineering approach to address a major challenge in two-dimensional (2D) transistors.
Published in?Nature Electronics, the study tackles a long-standing trade-off in atomically thin transistors. It's comparable to placing a traffic controller nearer to the road: control is enhanced, but the closer insulating material can also disrupt electron flow beneath it.?High-performance transistors require both precise control and seamless electron movement. Instead of looking for a new semiconductor, the researchers reengineered the atomic interface between the semiconductor and its insulator.
"Making the insulator thinner was only part of the challenge," stated Professor Wen-Hao Chang, the study's corresponding author at NYCU. "We also needed to safeguard the atomically thin semiconductor beneath. Our approach was to design an interface that accomplishes both, promoting uniform formation of the insulating layer and providing a buffer that maintains efficient electron flow."
A Difficult Trade-Off at the Atomic Scale
A transistor controls current flow through a semiconductor using a gate, separated by an insulating layer called the gate dielectric. As transistors shrink, this dielectric must become thinner to retain control. However, atomically thin semiconductors like molybdenum disulfide (MoS2) have surfaces without dangling bonds, complicating the uniform deposition of traditional insulators. Defects and electrical interactions from this can scatter electrons and lower carrier mobility. Therefore, the main challenge isn't just thinning the dielectric but also integrating a short channel and maintaining high carrier mobility, three factors that are difficult to optimize simultaneously in 2D transistors.?
Engineering a Better Connection
The NYCU-TSMC team addressed the issue by creating an ultra-thin layer between the semiconductor and its insulator. They initially applied a 0.3-nanometre-thick aluminium layer onto the atomically thin MoS2, then carefully transformed it into roughly 0.42 nanometres of aluminium oxide. This resulted in an extremely smooth, continuous surface with no tiny holes and minimal disruption to the semiconductor below. Although tiny, this layer plays two crucial roles. It first ensures the main insulating material forms a uniform, smooth coating; without it, insulation failed to fully cover the MoS2, leading to weak spots and potential electrical leakage. With this layer, coverage improved, and leakage decreased significantly. Second, it safeguards the fragile MoS2 from electrical disturbances caused by the insulator above, allowing electrons to flow efficiently through the transistor. Think of it as a precise connector between two materials that usually don't fit well, improving their connection without adding much to the transistor's thickness.
Strong Control Without Slowing Electrons
Using this approach, the researchers developed MoS2 transistors with an insulating layer equivalent to approximately one-nanometre-thick silicon dioxide. Despite this extreme thinness, the transistors efficiently conducted electrons and responded strongly to voltage changes, all while exhibiting low electrical leakage and stable operation. The key achievement was not any single performance metric but rather the combination of an ultra-thin insulator, precise control of the transistor, and a clear electron pathway. It's akin to narrowing a road without disrupting traffic flow - the engineered interface allows for tighter, more controlled structures without impeding electron movement.
According to Professor Tsung-En Lee of TSMC and NYCU, "When transistor components are just a few atomic layers thick, the interface becomes an integral part of the device, not just a boundary. Mastering atomic-level interface control could enable engineers to enhance transistors by improving material synergy, beyond just discovering new materials."
From the Laboratory Toward Larger-Scale Electronics
Researchers constructed their transistors using MoS2 grown by chemical vapor deposition (CVD), a technique that produces extremely thin layers across surfaces instead of using tiny flakes from crystals. This approach is especially promising for future development of large-area 2D semiconductors. However, significant challenges remain before this method can be used in commercial chip manufacturing. The current process involves complex steps like transferring MoS2, depositing materials in ultrahigh vacuum, and controlling oxidation carefully. Future efforts should focus on simplifying, scaling, and integrating these processes into existing semiconductor fabrication. The study reveals a broader opportunity: as transistors become atom-sized, material boundaries are no longer simple dividing lines but integral parts of the technology. While decades of research have centered on selecting materials for better transistors, this work suggests that we should also explore how to optimize the performance of already available materials, one atomic layer at a time.