As part of the research to improve the sophisticated metal-high-k gate stack for future logic devices, imec has demonstrated successfully higher-k dielectric with replacement metal gate (metal-gate-last) transistors, which realized a gate leakage reduction of 200x-1000x when compared to cutting-edge logic devices with HfO2 high-k gate dielectric.
Through in-depth process optimization efforts, imec realized tight electrical distribution to a gate length of down to 20 nm in order to handle the replacement metal gate’s process control and scalability for nano-scale devices. imec’s research provided basic understanding to work-function influences caused by metal intermixing in aggressively-scaled metal gates, thus dealing with a significant variability source in advanced transistors. A presentation on the research results was delivered at the VLSI Technology Symposium in Honolulu, Hawaii.
Since the scaling of three-dimensional transistors such as FinFETs into 14 nm and beyond is aggressively taking place, several transistor features advance towards scales of 10s-100s of atoms. imec’s state-of-the-art physical analysis laboratory carries out extensive research on advanced metrology and physical analysis. imec’s ability to use an innovative atom probe tomography method allows dopant distribution at atomic-scale resolution in nanoscale FinFETs.
Besides carrying out far-reaching research on improving the scalability of FinFETs and advanced gate stack, imec also concentrates on high-mobility channel transistors. imec demonstrated unprecedented pMOS performance with SiGe quantum well devices at the VLSI Technology Symposium. These devices hold potential to improve transistor performance better than present s strained-Si technology. These results were the outcome of imec’s key research program on CMOS technologies, in collaboration with its key partners programs, including Sony, Fujitsu, SK hynix, Elpida, TSMC, Samsung, Panasonic, Micron, INTEL and GLOBALFOUNDRIES.