A sophisticated planning and partitioning design flow for 3D stacked ICs has been co-developed by Imec and Atrenta.
Atrenta is one of the leading providers of SoC Realization solutions for application in the electronic systems and semiconductor markets. Both companies will demonstrate the 3D partitioning and planning design flow at the Design Automation Conference (DAC).
The demonstration will include backside redistribution layer routing support, through silicon via placement and design partitioning over a 3D stack along with routing congestion analysis. The companies will also exhibit thermal profiles integrated on the 3D design floor plan.
Several designers use 3D stacked ICs and their applications include solid-state drives, stacked DRAM, imagers, mobile products and other high-performance products. The ICs offer several benefits, including higher reuse and modularity and reduced footprint with faster and shorter interconnects. The products also enhance system integration at reduced cost.
To design cost-effective 3D devices and bring them to market more rapidly, a flow that allows precise partitioning and prototyping is important. The flow, developed by Atrenta and imec, reduces the number of design iterations and saves time and cost for exploring solution space.
Other important challenges faced in 3D design include mechanical stress and heat dissipation. Imec has created compact mechanical and thermal models to address these challenges and the models have been evaluated using 3D DRAM-on-logic packaged systems. The integration of imec’s stress models with design floor plans developed using the SpyGlass Physical 3D prototyping tool from Atrenta can help in assessing varied scenarios and an ideal option can be selected for full design implementation.
Source: http://www.atrenta.com/